SSM3K324R 2012-12-21 1 toshiba field-effect transistor silicon n-channel m os type ssm3k 324r power management switch applications dc-dc converter 1.8v drive low on-resistance: r ds(on) = 56 m ? (max) (@v gs = 4.5 v) : r ds(on) = 72 m ? (max) (@v gs = 2.5 v) : r ds(on) = 109 m ? (max) (@v gs = 1.8 v) absolute maximum ratings (ta = 25c) characteristic symbol rating unit drain-source voltage v dss 30 v gate-source voltage v gss 12 v drain current dc i d (note 1) 4.0 a pulse i dp (note 1,2) 10 power dissipation p d (note 3) 1 w t Q 10s 2 channel temperature t ch 150 c storage temperature range t stg - 55 to 150 c note: using continuously under heavy loads (e.g. th e application of high temperature/current/voltage and the significant cha nge in temperature, etc.) may cause this product to decrea se in the reliability significantly even if the operating con ditions (i.e. operating temperature/current/voltage, etc.) are wi thin the absolute maximum ratings. please design the appropriate reliability upon revie wing the toshiba semiconductor reliability handbook (handling precautions/derating concept and method s) and individual reliability data (i.e. reliabili ty test report and estimated failure rate, etc). note 1: the channel temperature should not exceed 1 50 c during use. note 2: pw Q 10ms,duty Q 1 note 3: mounted on a fr4 board. (25.4 mm 25.4 mm 1.6 mm, cu pad: 645 mm 2 ) marking equivalent circuit (top view) handling precaution when handling individual devices that are not yet m ounted on a circuit board, make sure that the envir onment is protected against electrostatic discharge. operator s should wear antistatic clothing, and containers a nd other objects that come into direct contact with devices should be mad e of antistatic materials. thermal resistance r th (ch-a) and power dissipation p d vary depending on board material, board area, boar d thickness and pad area. when using this device, please take h eat dissipation into consideration. unit: mm jedec D jeita D toshiba 2-3z1a weight: 11 mg (typ.) 1. gate 2. source 3. drain sot-23f kfd 1 2 3 1 2 3
SSM3K324R 2012-12-21 2 electrical characteristics (ta = 25c) characteristic symbol test conditions min typ. max unit drain-source breakdown voltage v (br) dss i d = 1 ma, v gs = 0 v 30 ? ? v v (br) dsx i d = 1 ma, v gs = - 12 v (note 5) 18 ? ? drain cut-off current i dss v ds = 24 v, v gs = 0 v ? ? 1 m a gate leakage current i gss v gs = 10 v, v ds = 0 v ? ? 10 m a gate threshold voltage v th v ds = 3 v, i d = 1 ma 0.4 ? 1.0 v forward transfer admittance ? y fs ? v ds = 3 v, i d = 2.0 a (note 4) ? 10.5 ? s drainCsource on-resistance r ds (on) i d = 2.0 a, v gs = 4.5 v (note 4) ? 45 56 m w i d = 1.0 a, v gs = 2.5 v (note 4) ? 55 72 i d = 0.5 a, v gs = 1.8 v (note 4) ? 69 109 input capacitance c iss v ds = 10 v, v gs = 0 v, f = 1 mhz ? 200 ? pf output capacitance c oss ? 40 ? reverse transfer capacitance c rss ? 13 ? total gate charge q g v ds = 10 v, i d = 2.4 a v gs = 4.5 v ? 2.2 ? nc gate-source charge q gs1 ? 0.5 ? gate-drain charge q gd ? 0.9 ? switching time turn-on time t on v dd = 10 v, i d = 2.0 a, v gs = 0 to 2.5v, r g = 4.7 w ? 9 ? ns turn-off time t off ? 9.5 ? drain-source forward voltage v dsf i d = -4.0 a, v gs = 0 v (note 4) ? -0.8 -1.2 v note 4: pulse test. note 5: if a reverse bias is applied between gate a nd source, this device enters v(br)dsx mode. note that the drain-source breakdown voltage is lowered in this m ode. usage considerations let v th be the voltage applied between gate and source tha t causes the drain current (i d ) to below (1 ma for the SSM3K324R). then, for normal switching operation, v gs(on) must be higher than v th, and v gs(off) must be lower than v th. this relationship can be expressed as: v gs(off) < v th < v gs(on). take this into consideration when using the device. 2.5v (b) v in (c) v out 0 v 10% 90% t on t off v dd v ds (on) t r t f 90% 10% (a) test circuit v dd = 10 v r g = 4.7 w duty 1% v in : t r , t f < 5 ns common source ta = 25c 0 2.5 v in out v dd 10 m s r g
SSM3K324R 2012-12-21 3 drainCsource voltage v ds (v) i d C v ds drain current i d (a) 0 0 0.4 0.6 0.8 6 2 4 0.2 8 10 v gs = 4.5 v 2.5 v 1.8 v 1 gateCsource voltage v gs (v) i d C v gs drain current i d (a) 0.0001 0 1 10 0.01 0.1 0.001 2.0 - 25 c common source v ds = 3 v pulse test 25 c 1.0 ambient temperature t a (c) r ds (on) C t a drainCsource on-resistance r ds (on) (m w ) 0 - 50 0 50 150 20 40 60 100 1.0 a / 2.5 v 100 common source pulse test 80 i d = 0.5 a / v gs = 1.8 v 2.0 a / 4.5 v t a = 100 c common source t a = 25 c pulse test r ds (on) C i d drain current i d (a) drainCsource on-resistance r ds (on) (m w ) 2.5 v 1.8 v v gs = 4.5 v common source t a = 25c pulse test 0 2 10 4 6 8 0 40 160 120 100 20 g k 60 80 140 r ds (on) C v gs drainCsource on-resistance r ds (on) (m w ) 0 2 gateCsource voltage v gs (v) 12 i d = 1.0 a common source pulse test 4 6 8 10 - 25 c 25 c t a = 100 c 0 40 160 120 100 20 g k 60 80 140 r ds (on) C v gs - 25 c 25 c drainCsource on-resistance r ds (on) (m w ) 0 2 gateCsource voltage v gs (v) 0 12 40 160 t a = 100 c 120 100 20 g k i d = 2.0 a common source pulse test 4 6 8 10 60 80 140
SSM3K324R 2012-12-21 4 drain current i d (a) forward transfer admittance ? y fs ? (s) |y fs | C i d 0.1 100 1.0 10 100 0.1 1 10 30 0.3 3.0 drainCsource voltage v ds (v) c C v ds total gate charge q g (nc) dynamic input characteristic gateCsource voltage v gs (v) 0 0 2 2 4 10 6 4 v th C t a gate threshold voltage v th (v) 0.8 0 - 50 0 150 0.2 0.4 0.6 1.0 50 100 ambient temperature t a (c) switching time t (ns) drain current i d (a) t C i d i dr C v ds common source v ds = 3 v t a = 25 c pulse test 0.01 common source v ds = 3 v i d = 1 ma capacitance c (pf) 10 0.1 1 10 100 1000 300 500 100 50 30 c iss 1 0.01 1 10 100 t f 10 0.1 t off t r t on 3 5 8 1 1000 common source t a = 25 c f = 1 mhz v gs = 0 v c oss common source i d = 2.4 a t a = 25 c v dd = 16 v v dd = 10 v c rss common source v dd = 10 v v gs = 0 to 2.5 v t a = 25 c r g = 10 w drain reverse current i dr (a) drainCsource voltage v ds (v) 0 1 10 0.01 0.1 0.001 -0.2 -0.6 -0.4 -1.0 -0.8 -1.2 common source v gs = 0 v pulse test g d s i dr - 25 c 25 c t a = 100 c
SSM3K324R 2012-12-21 5 pulse width t w (s) r th C t w transient thermal impedance r th (c/w ) 0.001 1000 0.01 0.1 1 100 10 100 1000 1 10 single pulse a. mounted on fr4 board (25.4 mm 25.4 mm 1.6 mm, cu pad: 645 mm 2 ) b. mounted on fr4 board (25.4 mm 25.4 mm 1.6 mm, cu pad: 0.72 mm 2 3) b a ambient temperature ta (c) p d C t a power dissipation p d (mw) 1600 0 400 120 100 140 800 160 80 60 40 20 0 -20 -40 a 1200 a: mounted on fr4 board (25.4mm 25.4mm 1.6mm , cu pad : 645 mm 2 ) b: mounted on fr4 board (25.4mm 25.4mm 1.6mm , cu pad : 0.72 mm 2 3) b
SSM3K324R 2012-12-21 6 restrictions on product use toshiba corporation, and its subsidiaries and affi liates (collectively "toshiba"), reserve the right to make changes to the information in this document, and related hardware, software an d systems (collectively "product") without notice. this document and any information herein may not b e reproduced without prior written permission from toshiba. even with toshiba's written permission, reproduction is permi ssible only if reproduction is without alteration/o mission. though toshiba works continually to improve produc t's quality and reliability, product can malfunctio n or fail. customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which minimize risk and avoid situations in which a malfunction or failure of product could ca use loss of human life, bodily injury or damage to property, including data loss o r corruption. before customers use the product, cre ate designs including the product, or incorporate the product into their own applications, customers must also refer to and comp ly with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and application notes for product and the precautions and conditions set forth in the "toshiba semiconductor reliability han dbook" and (b) the instructions for the application with which the pro duct will be used with or for. customers are solely responsible for all aspects of their own product design or applications, including but n ot limited to (a) determining the appropriateness o f the use of this product in such design or applications; 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